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loop optimization中文是什么意思

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  • Software pipelining ( swp ) is an effective technique for loop optimization
    软件流水是开发循环指令级并行的重要编译技术。
  • Provides local and global optimizations , automatic - register allocation , and loop optimization
    提供局部优化和全局优化、自动寄存器分配和循环优化。
  • Because loops are usually executed many times , loops optimization is a major aspect in optimal compilation
    摘要讨论了循环优化的目标和循环优化的各种程序变换方法。
  • Based on the hydraulic calculation model of pipe networks , a mathematical model of loop optimization is developed , which can make the optimal regulation of pipe networks to satisfy the design discharge of chilled water for all users
    摘要本文在管网水力计算模型的基础上,建立回路优化的数学模型,可以对管网进行优化调节,以使所有用户的水流量达到设计流量。
  • This paper discusses the target of loops optimization and various methods of program transformation which can significantly reduce the access time to subscripted variables , diminish some types of dependence , increase the " depth " of software pipelining , and merge some iterations of loops in order to make code compaction easier
    程序变换可大大减少下标变数的访问时间;消除某些类型的相关,提高软件流水的“深度” ;合并多个循环,有利于进行代码压缩。
  • Abstract : constant components and output opened ports in the result of high - level synthesis lead to explicit redundancy in gate - level technology mapping . explicit redundancy can not improve the performance , but increases power consumption , enlarges circuit area and decreases its testability , so it should be removed . this paper proposes a queue loop optimization algorithm to remove explicit redundancy completely which decreases the circuit area and improves the testability
    文摘:高级综合结果中常量元件和输出悬空端口导致门级工艺映射结果中存在显式冗余.显式冗余无助于提高电路性能,反而增加功耗,降低电路的可测试性,使电路面积增大,应予消除.文中提出了显式冗余的队列循环优化算法,完全消除了此类冗余,从而有效地减少了生成电路的基片面积,提高了电路的可测试性
  • Contrapose to the instability of the third - order charge - pump pll system , the loop optimization method is employed in system level design to decide the bandwidth and phase margin , therefore the loop bandwidth locates at the maximum phase margin to guarantee the stability of the system . according to tsmc 0 . 35 m sige bicmos model , the sub - circuits in the designed pll and the whole system are simulated and verified by the cadence spectre
    5 .根据tsmc0 . 35 msigebicmos工艺模型,利用cadencespectre模拟软件对所设计的电荷泵锁相环路中各个模块及整个系统进行了模拟仿真,模拟结果显示,在1 . 5v电源电压下,频率为200mhz的参考输入信号,输出中心频率为800mhz ,分频电路采用4分频,环路带宽为10mhz ,捕获时间大约为0 . 92 s ,功耗大约为15mw ,达到了设计指标。
  • 百科解释
In compiler theory, loop optimization is the process of the increasing execution speed and reducing the overheads associated of loops. It plays an important role in improving cache performance and making effective use of parallel processing capabilities.
详细百科解释
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Last modified time:Wed, 13 Aug 2025 00:29:56 GMT

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